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RT8465 ? ds8465-01 march 2013 www.richtek.com 1 copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. ? constant voltage high power factor pwm boost driver controller for mr16 application applications z mr16, ar111 lamps z pfc controller general description the RT8465 is a constant output voltage, active high power factor, pwm boost driver controller. it can be used as the first boost stage followed by a constant current buck converter with input from ac/electronic transformer in mr16/ar111 application. to achieve high power factor, the ac input voltage from ac/electronic transformer is sensed via the sin pin. an internal power factor correction circuit follows the sensed sine waveform and modulates the external mosfet duty cycle-by-cycle to achieve constant output voltage. the output voltage is adjustable via an output resistive divider. by operating at 220khz, the filter component size can be small to fit in tight mr16 space. to drive industrial grade mosfet switches, the RT8465 gate driver can deliver up to 0.8a output current with 9v gate output voltage. features z z z z z wide input voltage range : 8v to 32v z z z z z high power factor correction with simple system circuits z z z z z adjustable constant output voltage z z z z z built-in high power factor correction circuit z z z z z typical 250 a start-up supply current z z z z z low quiescent current : 0.1 a z z z z z sop-8 package z z z z z rohs compliant and halogen free simplified application circuit RT8465 sin fb icomp vcomp vcc gate gnd sense r5 c5 r4 c4 c3 r2 r3 rs m1 r1 c2 ac in d1 c1 d2 + ~ - l
RT8465 2 ds8465-01 march 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. ? functional pin description pin no. pin name pin function 1 gnd ground. 2 gate gate driver for external mosfet switch. 3 vcc power supply. for good bypass, place a ceramic capacitor near the vcc pin. 4 sense inductor current sense input. the inductor current is sensed by a resistor between gnd and sense pins. the sense pin signal is used as the saw tooth signal to the pwm comparator. the comparator output will modulate the gate turn-on duty to achieve the output voltage regulation. 5 fb output voltage sense input. the output voltage is sensed through an external resistive divider. the sensed voltage (which is tied to amplifier negative input) is compared to an internal reference threshold at 1.2v (which is tied to amplifier positive input). 6 icomp output of the multiplier. to achieve high power factor, the voltage loop amplifier output signal is modulated with the sensed input voltage through the sin pin by an internal multiplier. a compensation network between icomp and gnd is needed. 7 sin input power voltage sensing for pfc function. an external resistor for input voltage sensing is connected to the power input. 8 vcomp output of the internal voltage loop gm amplifier. a compensation network between vcomp and gnd is needed. ordering information note : richtek products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. package type s : sop-8 RT8465 lead plating system z : eco (ecological element with halogen free and pb free) pin configurations sop-8 (top view) gnd gate vcc sense vcomp sin fb icomp 2 3 4 5 6 7 8 marking information RT8465zs : product number ymdnn : date code RT8465 zsymdnn
RT8465 3 ds8465-01 march 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. ? function block diagram operation the RT8465 is a floating-gnd boost pwm current mode controller with an integrated low side floating gate driver. the start up voltage of RT8465 is around 10v. once vcc is above 10v, the RT8465 will maintain operation until vcc drops below 8v. the RT8465's main control loop consists of a 220khz fixed frequency oscillator, an internal 1.2v feedback (fb) voltage sense threshold, and the pfc control circuit with a pwm comparator. in normal operation, the gate turns high when the gate driver is set by the oscillator (osc). when the feedback (fb) voltage is below the reference 1.2v threshold, the vcomp pin voltage will go high. the icomp signal is the result of vcomp signal multiplied with sin signal. higher icomp voltage means longer gate turn-on period. the gate does not always turn off in each cycle. the gate will be turned on again by osc for the next switching cycle. the RT8465 provides several protections, including input voltage under voltage lockout (uvlo), over current protection (ocp) and vcc over voltage protection (ovp). additionally, to ensure the system reliability, the RT8465 is built with internal thermal protection function. vcc gnd icomp + - + - 10v/8v chip enable s q r r osc pwm control circuit pfc control circuit 8v + ovp 200k + - 35v 1.2v vcomp fb gate sense sin
RT8465 4 ds8465-01 march 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. ? electrical characteristics recommended operating conditions (note 4) z supply input voltage, vcc ---------------------------------------------------------------------------------------------- 8v to 32 v z junction temperature range -------------------------------------------------------------------------------------------- ? 40 c to 125 c z ambient temperature range -------------------------------------------------------------------------------------------- ? 40 c to 85 c (v cc = 24v dc , c load = 1nf, r load = 2.2 in series, t a = 25 c, unless otherwise specified) absolute maximum ratings (note 1) z vcc, sin to gnd ---------------------------------------------------------------------------------------------------------- ? 0.3v to 40v z gate to gnd (note 6) ------------------------------------------------------------------------------------------------- ? 0.3v to 16v z vcomp, icmop to gnd ------------------------------------------------------------------------------------------------ ? 0.3v to 4v z fb to gnd ------------------------------------------------------------------------------------------------------------------ ? 0.3v to 2v z sense to gnd ------------------------------------------------------------------------------------------------------------ ? 1v to 0.3v z power dissipation, p d @ t a = 25 c sop-8 ------------------------------------------------------------------------------------------------------------------------ 0.53w z package thermal resistance (note 2) sop-8, ja ------------------------------------------------------------------------------------------------------------------ 188 c/w z junction temperature ----------------------------------------------------------------------------------------------------- 150 c z lead temperature (soldering, 10 se c.) ------------------------------------------------------------------------------- 260 c z storage temperature range -------------------------------------------------------------------------------------------- ? 65 c to 150 c z esd susceptibility (note 3) hbm (human body model) ---------------------------------------------------------------------------------------------- 2kv mm (ma chine model) ----------------------------------------------------------------------------------------------------- 200v parameter symbol test conditions min typ max unit input start-up voltage v st -- 10 11 v under voltage lockout threshold v uvlo 7 8 -- v under voltage lockout threshold hysteresis v uvlo -- 2 -- v input supply current i cc after start-up, v cc = 24v -- 2 5 ma input quiescent current i qc before start-up, v cc = 7v -- 0.1 -- a oscillator switching frequency f sw v sin = 14v 190 220 250 khz maximum duty in transient operation d max(tr) vc = 3v -- -- 100 % maximum duty in steady state operation d max -- 97 -- % blanking time t blank 200 -- -- ns minimum turn-off time (note 5) -- 650 -- ns current sense amplifier current sense voltage v sense v comp = 1v, s in = 15v -- ? 100 -- mv sense input current i sense sense = 100mv (note 5) -- 10 -- a
RT8465 5 ds8465-01 march 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. ? note 1. stresses beyond those listed ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions may affect device reliability. note 2. ja is measured at t a = 25 c on a high effective thermal conductivity four-layer test board per jedec 51-7. note 3. devices are esd sensitive. handling precaution is recommended. note 4. the device is not guaranteed to function outside its operating conditions. note 5. guaranteed by design; not subject to production test. note 6. the gate voltage is internally clamped and varies with operating conditions. parameter symbol test conditions min typ max unit gate driver output gate pin maximum voltage v gate no load at gate pin -- 9.5 16 v i gate = ? 20ma -- 9.1 -- high v gate_h i gate = ? 100 a -- 9.4 -- v i gate = 20ma -- 0.75 -- gate voltage low v gate_l i gate = 100 a -- 0.5 -- v gate drive rise and fall time 1nf load at gate -- 70 100 ns gate drive source and sink peak current 1nf load at gate (note 4) -- 0.5 0.8 a multiplier v sin = 14v 50 60 70 sin pin input current v sin = 28v 80 100 120 a icomp threshold for pwm switch off v icomp -- 1.2 -- v vc output current i vcomp 0.5v vc 2.4v (note 5) -- 16 -- a feedback voltage v fb 1.1 1.2 1.3 v feedback input current i fb v fb = 1.2v (note 5) -- 1 -- a ovp and soft-start over voltage protection v ovp vcc pin 32 35 38 v thermal protection thermal shutdown temperature t sd -- 150 -- c sin pin input resistance -- 200 -- k
RT8465 6 ds8465-01 march 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. ? typical application circuit cc converters : rt8450/rt8471/rt8463 cc drivers : rt8482/rt8458d RT8465 sin fb icomp vcomp vcc gate gnd sense 3 2 1 4 7 5 6 8 r5 c5 r4 c4 c3 r2 r3 rs m1 r1 c2 electronic transformer 12v ac input d1 d2 + ~ - l load : const current /const voltage gnd c1
RT8465 7 ds8465-01 march 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. ? vcc_ovp vs. temperature 32 33 34 35 36 37 38 -50-25 0 25 50 75100125 temperature (c) v ovp (v) vcc supply current vs. input voltage 1.4 1.5 1.6 1.7 1.8 1.9 2.0 8 1318232833 input voltage (v) supply current (ma ) typical operating characteristics vcc supply current vs. temperature 0.0 0.5 1.0 1.5 2.0 2.5 -50 -25 0 25 50 75 100 125 temperature (c) supply current (ma ) v cc = 24v uvlo vs. temperature 5 7 9 11 13 15 -50-25 0 25 50 75100125 temperature (c) uvlo (v) uvlo-h uvlo-l fb voltage vs. temperature 1.1 1.2 1.2 1.3 1.3 -50-25 0 25 50 75100125 temperature (c) fb voltage (v) v cc = 24v gate voltage high vs. temperature 6 7 8 9 10 11 12 -50 -25 0 25 50 75 100 125 temperature (c) gate voltage (v) v cc = 24v i gate = ? 20ma i gate = ? 100 a
RT8465 8 ds8465-01 march 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. ? gate voltage low vs. temperature 0.0 0.2 0.4 0.6 0.8 1.0 -50 -25 0 25 50 75 100 125 temperature (c) gate voltage (v) v cc = 24v i gate = 20ma i gate = 100 a switching frequency vs. input voltage 180 190 200 210 220 230 81318232833 input voltage (v) switching frequency (khz) 1 v sin = 2v v sin = 14v minimum on-time vs. temperature 250 270 290 310 330 350 -50-25 0 25 50 75100125 temperature (c) minimum on-time (ns ) v cc = 24v sin voltage vs. v sense threshold 0 100 200 300 400 500 600 700 0 5 10 15 20 25 30 sin voltage (v) v sense threshold (mv) v cc = 24v v comp = 2.5v v comp = 2.2v v comp = 1.9v v comp = 1.6v v comp = 1.3v v comp = 1v v comp = 0.7v sin input current vs. input voltage 0 10 20 30 40 50 60 70 8 1318232833 input voltage (v) sin current ( a) v sin = 2v v sin = 14v v sense threshold vs. temperature -0.20 -0.15 -0.10 -0.05 0.00 0.05 0.10 -50-25 0 25 50 75100125 temperature (c) v sense threshold (v) v cc = 24v, v comp = 3v v sin = 20v v sin = 10v v sin = 5v
RT8465 9 ds8465-01 march 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. ? application information the RT8465 provides active power factor correction for power systems with fewer external components. the RT8465 can operate in both continuous conduction mode (ccm) and discontinuous conduction mode (dcm) by fixed frequency pwm control. the fixed switching frequency is internally set at 220khz. the ic operates with a dual control topology; the inner current loop and the outer voltage loop. the inner current loop of the ic controls the sinusoidal profile for the average input current. it uses the dependency of the pwm duty cycle on the line input voltage to determine the corresponding input current. this means the average input current follows the input voltage as long as the device operates in ccm. under light load condition, depending on the choke inductance, the system may enter dcm. in dcm, the average current waveform will be distorted but the resultant harmonics are still low enough to meet the standard of iec61000-3-2. the RT8465 employs average current control to achieve a better input current waveform. in figure 1, the inductor current is sensed and filtered by a current error amplifier of which output drives a pwm modulator. in this way, the inner current loop tends to minimize the error between the average input current i in and its reference. the converter works in ccm, so the same considerations done with regard to the peak current control can be applied. multiplier the multiplier has two inputs. the sin pin is the divided sinusoidal voltage which makes the current sense comparator threshold voltage vary from zero to peak value. the other input is the output of error amplifier at vcomp pin. in this way, the input average current wave will be sinusoidal as well as reflects the load status. in order to achieve high power factor and good thd achieved, the multiplier transfer character is designed to be linear over a wide dynamic range, namely, 1v to 20v for sin and 0.8v to 1.2v for fb. the relationship between the multiplier output and inputs is described as the below equation : figure 1 . functional block with pfc ccm control pulse width modulator the ic employs an average current control scheme in ccm to achieve the power factor correction. if the voltage loop is working and output voltage is kept constant, the duty cycle, d off , for a ccm pfc system is given as from the above equation, d off is proportional to vin. the objective of the current loop is to regulate the average inductor current such that it is proportional to the duty cycle, d off , and the input voltage, v in . figure 2 shows the waveform for the control scheme. in off out v d = v i in, avg ( ) ? icomp comp sin v = kv 0.7v where v icomp is the reference for the current sense, k is the multiplier gain, vcomp is the error amplifier output voltage and v sin is the sinusoidal reference voltage on pin 7. i ac v ac + - i in l + - r sense v in sinusoidal reference s 1 k voltage error amplifier 220khz + - multiplier r5 c5 fb vcomp icomp sin r2 r3 gate pwm modulator v out c1 + - r out sense + ~ - d1 i out v ref m1 s r q
RT8465 10 ds8465-01 march 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. ? the pwm is performed by the intersection of a ramp signal with the current error amplifier output. the pwm cycle starts with the gate turn on for a minimum duration about 300ns typical. in case of the inductor current reaches the peak current limitation, the gate will be turned off immediately when v sense is triggered. error amplifier the outer voltage loop of the cascaded control scheme regulates the pfc output bus voltage v out . the internal reference on the non-inverting input of the error amplifier is 1.2v. the error amplifier's inverting feedback fb is connected to an external resistor divider which senses the output voltage. the output of the error amplifier is one of the two inputs of the multiplier. a compensation loop is connected outside between the error amplifier output at the vcomp pin, and ground of the gnd pin. normally, the compensation loop bandwidth is very low to realize high power factor for pfc converter. the compensation is also responsible for the soft start function which controls an increasing ac input current during start-up. + - r5 c5 fb vcomp ?? ?? ?? out r3 v r2 + r3 1.2v figure 3 . voltage loop amplifier current sense/current sense comparator the pfc switch's turn-on current is sensed through an external resistor in series with the switch. when the sensed voltage exceeds the threshold voltage (the multiplier output), the current sense comparator will become low and the external mosfet will be turned off. this ensures a cycle-by-cycle current mode control operation. the maximum current sense reference is 1.8v. the max value usually occurs in start-up process or abnormal conditions such as short load. under voltage lockout (uvlo) the RT8465 internal uvlo block monitors the vcc power supply with 2v hysteresis. the hysteresis behavior guarantees a one-short startup resistor and hold-up capacitor. the ic will then be consuming typically 150 a when start-up and the power dissipation on resistor would be less than 0.1w. after start-up, the operating current is typically 1.5ma to get a better efficiency. over voltage protection (ovp) whenever v out exceeds the rated value by 5%, the over voltage protection is activated. this is implemented by sensing the voltage at fb pin with respect to a reference voltage of 1.2v. this results in a lower input power to reduce the output voltage v out . figure 4 . state of power v cc operation i in, avg i in ramp profile gate drive t figure 2 . average current controls in ccm off start up normal operation open loop/ standby normal operation off 10v 8v v cc t ic's state
RT8465 11 ds8465-01 march 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. ? figure 5. derating curve of maximum power dissipation thermal considerations for continuous operation, do not exceed absolute maximum junction temperature. the maximum power dissipation depends on the thermal resistance of the ic package, pcb layout, rate of surrounding airflow, and difference between junction and ambient temperature. the maximum power dissipation can be calculated by the following formula : p d(max) = (t j(max) ? t a ) / ja where t j(max) is the maximum junction temperature, t a is the ambient temperature, and ja is the junction to ambient thermal resistance. for recommended operating condition specifications, the maximum junction temperature is 125 c the junction to ambient thermal resistance, ja , is layout dependent. for sop-8 package, the thermal resistance, ja , is 188 c/w on a standard jedec 51-7 four-layer thermal test board. the maximum power dissipation at t a = 25 c can be calculated by the following formula : p d(max) = (125 c ? 25 c) / (188 c/w) = 0.53w for sop-8 package the maximum power dissipation depends on the operating ambient temperature for fixed t j(max) and thermal resistance, ja . the derating curve in figure 5 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation. figure 6. pcb layout guide gnd gate vcc sense vcomp sin fb icomp 2 3 4 5 6 7 8 r vc c vc r3 c2 r4 v out gnd gnd c out d1 gate pgnd d2 c1 r2 c2 pgnd sin v in v cc v out c in 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0 25 50 75 100 125 ambient temperature (c) maximum power dissipation (w) 1 four-layer pcb
RT8465 12 ds8465-01 march 2013 www.richtek.com richtek technology corporation 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 richtek products are sold by description only. richtek reserves the right to change the circuitry and/or specifications without notice at any time. customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a richtek product. information furnish ed by richtek is believed to be accurate and reliable. however, no responsibility is assumed by richtek or its subsidiaries for its use; nor for any infringeme nts of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of r ichtek or its subsidiaries. outline dimension a b j f h m c d i 8-lead sop plastic package dimensions in millimeters dimensions in inches symbol min max min max a 4.801 5.004 0.189 0.197 b 3.810 3.988 0.150 0.157 c 1.346 1.753 0.053 0.069 d 0.330 0.508 0.013 0.020 f 1.194 1.346 0.047 0.053 h 0.170 0.254 0.007 0.010 i 0.050 0.254 0.002 0.010 j 5.791 6.200 0.228 0.244 m 0.400 1.270 0.016 0.050

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